(a) Fields of the Invention
The present invention relates to semiconductor-element mounting substrates for mounting semiconductor elements (referred hereinafter to as IC chips), semiconductor devices, and electronic equipment.
(b) Description of Related Art
With a recent trend toward high-density mounting of IC chips, resin-sealed semiconductor devices with a great number of electrodes have been developed. In mounting IC chips to surface mount type semiconductor devices of these types, large stress is generated between the IC chip and a die pattern because a resin substrate greatly differs in thermal expansion coefficient from sealing resin and a gold-plated copper pattern serving as the die pattern. This stress warps the resin substrate. As a result of this, the IC chip exfoliates from the die pattern to degrade the reliability of the semiconductor device, which has conventionally been a problem. Here is a list of the thermal expansion coefficients of the resin substrate, the die pattern, and the sealing resin: glass epoxy resin commonly employed as the resin substrate has a thermal expansion coefficient of 14 ppm/° C.; thermosetting resin employed for the sealing resin has a thermal expansion coefficient of 16 ppm/° C.; and a copper pattern generally employed as the die pattern has a thermal expansion coefficient of 17 ppm/° C. As shown in this list, since the thermal expansion coefficient of the resin substrate differs from those of the die pattern and the sealing resin, large stress is generated between the IC chip and the die pattern.
In addition, the IC chip is bonded to the die pattern through a die bonding material made of, for example, epoxy resin-based conductive adhesive. According to the material used for the target to be bonded, the adhesive strength of the die bonding material varies greatly. For example, it is known that if the IC chip is bonded through the die bonding material to a gold-plated film formed on the surface of the die pattern, the adhesive strength of the die bonding material is small. However, typically, on the surface of the die pattern, formation of the gold-plated film is required. Therefore, if the IC chip is bonded onto this gold-plated film with conductive adhesive as a die bonding material, the IC chip is likely to exfoliate during a fabrication process of the semiconductor device or during the step of solder-reflow mounting of the semiconductor device to a circuit board. Such exfoliation causes breaks in wire-bonded wire leads or traces of an interconnection pattern to seriously damage the reliability of the semiconductor device. In particular, such exfoliation of the IC chip occurs more noticeably as the size of the IC chip relative to the size of a package increases.
As an approach to addressing the above-mentioned problem of degradation in the reliability of the semiconductor device, for example, a semiconductor device having the structure shown below is disclosed (see, for example, Japanese Unexamined Patent Publication No. 2002-329807 (referred hereinafter to as Document 1)). The semiconductor device includes: a resin substrate; a die pattern formed on the resin substrate; an interconnection pattern formed around the die pattern; an IC chip mounted above the die pattern; and a thin conductive wire connecting the IC chip and the interconnection pattern. The die pattern has a main pattern, a bonding pattern, and a joining pattern. The main pattern has a smaller outer size than the IC chip. The bonding pattern is arranged outside the mounting position of the IC chip. The joining pattern connects the main pattern and the bonding pattern. The resin substrate has an insulative coating at least at the corners of the IC chip and corresponding portions.
Document 1 discloses the following approach as the advantage of the semiconductor device shown above. The thermal expansion coefficient of the resin substrate differs from those of the die pattern and the sealing resin. Thereby, even though thermal strain is concentrated at the corners of the IC chip, the corners are bonded through the die bonding material to the insulative coating with a large adhesive strength. This prevents the corners of the IC chip from exfoliating from the resin substrate, which significantly improves the reliability of the semiconductor device.
For example, Japanese Unexamined Patent Publication No. 2005-136329 (referred hereinafter to as Document 2) discloses a semiconductor device having the structure shown below. The main surface of a substrate is formed with a first region, a second region surrounding the first region, and a third region surrounding the second region. The first region is provided with a first insulative coating with no corners. The top of the first insulative coating is provided with an IC chip. The IC chip is covered with sealing resin. The third region of the substrate is provided with a second insulative coating. The bottom surface of the IC chip covers the first region.
In the case of the semiconductor device having this structure, the insulative coating is provided only over the first region and the third region, and not provided over a region immediately below the outer edge of the IC chip and its vicinity. Document 2 discloses the following fact: a main factor behind interconnection breaks is that according to temperature cycling, stress is repeatedly applied to the insulative coating arranged over the outer edge region of the IC chip and its vicinity, and however the semiconductor device having the structure shown above can reduce the stress applied to the insulative coating in this region to avoid interconnection breaks.